Want to work in an innovative high-tech French company? With an agile and motivated software team?
Join a dynamic and fast-growing high-tech scale-up!
Created in 2008, as a spin-off of the CEA, Kalray has become a leader in developing massively parallel manycore processors. Kalray’s revolutionary MPPA® processor features several hundred cores that run in parallel, delivering high performance, low power and real-time data processing. These intelligent processors are being extensively deployed in fast-growing sectors such as new-generation networks (intelligent datacenters) and autonomous vehicles, as well as healthcare, drones and robots. Our customers and partners include industry leaders from around the globe. Along with our processor family, Kalray offers electronic boards, software development kits (SDK), application software and libraries that allow our customers to develop their own applications.
For our H/W & Test/Product Engineering team we are recruiting an Engineer in charge of the Design-For-Test (DFT) strategy and DFT implementation on the new generation of the MPPA processor.
You will be involved at the begining of the project, in parallel of the design front-end activities.
From the DFT requirements established by the Test/Product Engineering, you will implement the appropriate controlability/observability in order to reach the best coverage with a minimum of pattern vectors.
Your will be in charge of test pattern generation and support the test engineering team for patterns debug during bring-up.
- 5 years+ experience of DFT implementation in complex SoCs
- Experience of SoC architecture would be a plus
- Superior knowlege of DFT implementation (Scan insertion, MBIST, boundary scan, IJTAG/JTAG)
- Valuable experience of DFT Mentor environement (Tessent)
- Strong technical lead
- Highly Responsive
Type of contract: Permanent /full-time
Location: Montbonnot (Grenoble area, France) or Sophia-Antipolis (Nice area, France).