HW-2021-J-07 – Junior RTL Designer

Kalray (Euronext Growth Paris – FR0010722819 – ALKAL) is a fabless semiconductor company, pioneer in a new generation of processors for intelligent systems. MPPA® Intelligent processors are able to capture and analyze on the fly massive data flows, close to where they are generated, and interact in real time with the outside world. These processors are capable of running demanding AI algorithms and simultaneously a wide set of different processing and control tasks such as mathematical algorithms, signal processing, network or storage software stacks. Kalray’s Intelligent Processors can be deployed in fast-growing sectors of Edge Computing and AI: Modern data centers, networks (5G), autonomous vehicles, healthcare equipment, industry 4.0, drones and robots… Kalray’s offering includes processors, system boards and a software suite, for a broad spectrum of customers such as data storage systems and compute server manufacturers, intelligent system integrators and consumer product manufacturers such as car makers. Founded in 2008 as a spin-off of CEA French lab, Kalray counts among its investors: Alliance Venture (Renault-Nissan-Mitsubishi), Safran, NXP Semiconductors, CEA and Bpifrance.

To support our growth, we are recruiting a Junior RTL Designer for our Hardware Team.


You will be part of the Hardware team, who is in charge of the full development of the new generation of our high performance processors in very advanced technology nodes. You role will encompass the specification, the micro architecture, the design, the synthesis and the pre & post Tape Out validation.  You will interact with many teams including Business Units, Verification, BackEnd, Board and SW teams.

You are passionate about hardware digital design and how to turn customer and application requirements into a chip.



  • 2+ years of experience in ASIC digital RTL for commercial products
  • 1GHz+ ASIC design would be a plus


  • Digital RTL design (VHDL / Verilog)
  • Knowledge of Clock and reset scheme
  • Knowledge of synthesis constraints writing
  • Knowledge of CDC structure would be a plus
  • Knowledge of Synthesis and formal proof Flow would be a plus
  • Fluent in technical English
  • Good communication / reporting skills


  • Graduate engineer or equivalent
  • Curious, Rigorous, Autonomous

Starting date: As soon as possible

Type of contract: Permanent / full-time

Location: Montbonnot (Grenoble area – France) or Sophia Antipolis (Canne / Nice area – France)

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