MPPA® DPU ARCHITECTURE
A MASSIVELY PARALLEL PROCESSOR ARRAY ARCHITECTURE
Kalray MPPA® DPU Manycore
A Massively Parallel Processor Array Architecture
The world is facing an explosion of data which current technologies were not initially designed for and cannot always handle efficiently. Industry needs a new type of processor. Enter the era of Intelligent DPU (Data Processing Unit) Processors.
The overall architecture of the Kalray 3rd generation of MPPA® DPU (Data Processing Unit) processor aka Coolidge™ is based on a “Massively Parallel Processor Array” architecture, which is characterized by the association of computing clusters connected to each other, to the external memory and to the I/O interfaces via two independent interconnects.
The MPPA® DPU’s interconnects are suited to different types of data transfers. The first interconnect is an AXI Fabric bus grid, for use read/write access from cores to memories and peripherals connected by PCIe. The second interconnect by an RDMA NoC (Network-on-Chip), that supports data transfers to or from the Ethernet network interfaces and connect all clusters together.
The robust partitioning necessary for safe operation of the processor is carried out at the granularity of the computing cluster and is based on the configuration of memory management units (MMUs), memory protection units (MPUs), and on the deactivation or not of network on chip links.
MPPA® DPU Unique Architecture
(Data Processing Unit)
The Coolidge™ DPU (Data Processing Unit) processor cluster is partitioned between a secure area and an user application area. The secure area includes a core (RM core) dedicated to security and safety functions, associated with an isolated memory bank.
The user application zone brings together 16 processing cores (PE cores) and a data movement engine (DMA) connected to a 4MB local memory called SMEM and composed of 16 banks.
The 16 processing cores operates in two modes:
- An SMP (Symetric Multi-Processing) mode intended for high performance applications, where the PE cores behave like a multicore processor CPU.
- An AMP (“Assymetric Multi-Processing”) mode intended for real-time applications, where the ¨PE cores behave like sixteen independent single-core CPUs.
COOLIDGE™ MPPA® DPU Processor
The Massively Parallel Processor Array (MPPA®) is Kalray’s ground-breaking manycore technology, giving DPU chips more processing power with less power consumption.
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This Kalray presentation describes Kalray’s KV3 VLIW core (key component of the MPPA® DPU processor) and experience in the development of its LLVM compiler backend.