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  • Key features of the MPPA® Coolidge.

  • Find out what's unique about the MPPA® (Massively Parallel Processor Array) architecture.

  • Key features of the K200-LP card.

  • Key features of Kalray Flashbox NVMe All-Flash Array.

  • Find out how the Kalray Flashbox is revolutionizing storage.

  • Find out how the Kalray's Smart Storage Adapter can be used for composable architectures and disaggregation.

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  • "A Qualitative Approach to Many-core Architecture” in "Multi-Processor System-on-Chip 1 Architectures", Benoît Dupont de Dinechin, Book ISBN: 9781789450217, March 2021.
  • "Study and Comparison of Hardware Methods for Distributing Memory Bank Accesses in Many-core Architectures" in "Multi-Processor System-on-Chip 1 Architectures", Arthur Vianes, Frédéric Rousseau, Book ISBN : 9781789450217, March 2021.
  • "Novel Arithmetics in Deep Neural Networks Signal Processing for Autonomous Driving: Challenges and Opportunities", Marco Cococcioni, Federico Rossi, Emanuele Ruffaldi, Sergio Saponara, Benoît Dupont de Dinechin, IEEE Signal Process. Mag. 38(1): 97-110, 2021.
  • "Classification Error Approximation of a Compressed Linear Softmax Layer", Conference Paper - 29th European Signal Processing Conference (EUSIPCO 2021), Diana Resmerita, Rodrigo Cabral Farias, Lionel Fillatre, Benoît Dupont de Dinechin,  August 2021.


  • Bounding the delays of the MPPA network-on-chip with network calculus: Models and benchmarks. Marc Boyer, Amaury Graillat, Benoît Dupont de Dinechin, Jörn Migge. Perform. Evaluation 143: 102124 (2020)
  • Deep Learning Inference on the MPPA3 Manycore Processor. Benoit Dupont de Dinechin - Embedded World Conference 2020
  • Scaling Up the Memory Interference Analysis for Hard Real-Time Many-Core Systems. Maximilien Dupont de Dinechin, Matheus Schuh, Matthieu Moy, Claire Maiza, 2020
  • A study of predictable execution models implementation for industrial data-flow applications on a multi-core platform with shared banked memory. Matheus Schuh, Claire Maiza, Joël Goossens, Pascal Raymond, Benoît Dupont de Dinechin. RTSS 2020
  • Certified and efficient instruction scheduling: application to interlocked VLIW processors. Cyril Six, Sylvain Boulmé, David Monniaux. Proc. ACM Program. Lang. 4(OOPSLA): 129:1-129:29 (2020)