Resources
Academic Research and Publications
2023
- IN-PLACE MULTICORE SIMD FAST FOURIER TRANSFORMS. HPEC 2023 – 27TH ANNUAL IEEE HIGH PERFORMANCE EXTREME COMPUTING VIRTUAL CONFERENCE, SEP 2023, VIRTUAL CONFERENCE, UNITED STATES. BENOÎT DUPONT DE DINECHIN, JULIEN HASCOET, OREGANE DESRENTES.
- EXACT FUSED DOT PRODUCT ADD OPERATORS. 2023 ARITH – 30TH IEEE INTERNATIONAL SYMPOSIUM ON COMPUTER ARITHMETIC, SEP 2023, PORTLAND, OR, UNITED STATES. OREGANE DESRENTES, BENOIT DUPONT DE DINECHIN, FLORENT DE DINECHIN.
- EXACT DOT PRODUCT ACCUMULATE OPERATORS FOR 8-BIT FLOATING-POINT DEEP LEARNING. DSD/SEAA 2023 – 26TH EUROMICRO CONFERENCE SERIES ON DIGITAL SYSTEM DESIGN, SEP 2023, DURRES, ALBANIA. OREGANE DESRENTES, BENOIT DUPONT DE DINECHIN, JULIEN LE MAIRE.
2022
- “COMPUTING IN-PLACE FFTS WITH SIMD LANE SLICING”, IEEE HIGH PERFORMANCE EXTREME COMPUTING CONFERENCE (HPEC) 2022, SEPTEMBER 2022. BENOÎT DUPONT DE DINECHIN
- “A POSIT8 DECOMPRESSION OPERATOR FOR DEEP NEURAL NETWORK INFERENCE.” CONGA 2022: 14-30, ORÉGANE DESRENTES, DIANA RESMERITA, BENOÎT DUPONT DE DINECHIN.
- ‘COMPUTING IN-PLACE FFTS WITH SIMD LANE SLICING.’ IN IEEE HIGH PERFORMANCE EXTREME COMPUTING CONFERENCE, HPEC 2022, WALTHAM, MA, USA, SEPTEMBER 19-23, 2022, 1–7, 2022. BENOÎT DUPONT DE DINECHIN.
2021
- “ENGINEERING A MANYCORE PROCESSOR FOR EDGE COMPUTING,” B. DUPONT DE DINECHIN, 2021 10TH MEDITERRANEAN CONFERENCE ON EMBEDDED COMPUTING (MECO), 2021, PP. 1-1.
- “A QUALITATIVE APPROACH TO MANY-CORE ARCHITECTURE” IN “MULTI-PROCESSOR SYSTEM-ON-CHIP 1 ARCHITECTURES”, BENOÎT DUPONT DE DINECHIN, BOOK ISBN: 9781789450217, MARCH 2021.
- “STUDY AND COMPARISON OF HARDWARE METHODS FOR DISTRIBUTING MEMORY BANK ACCESSES IN MANY-CORE ARCHITECTURES” IN “MULTI-PROCESSOR SYSTEM-ON-CHIP 1 ARCHITECTURES”, ARTHUR VIANES, FRÉDÉRIC ROUSSEAU, BOOK ISBN : 9781789450217, MARCH 2021.
- “NOVEL ARITHMETICS IN DEEP NEURAL NETWORKS SIGNAL PROCESSING FOR AUTONOMOUS DRIVING: CHALLENGES AND OPPORTUNITIES“, MARCO COCOCCIONI, FEDERICO ROSSI, EMANUELE RUFFALDI, SERGIO SAPONARA, BENOÎT DUPONT DE DINECHIN, IEEE SIGNAL PROCESS. MAG. 38(1): 97-110, 2021.
- “CLASSIFICATION ERROR APPROXIMATION OF A COMPRESSED LINEAR SOFTMAX LAYER”, CONFERENCE PAPER – 29TH EUROPEAN SIGNAL PROCESSING CONFERENCE (EUSIPCO 2021), DIANA RESMERITA, RODRIGO CABRAL FARIAS, LIONEL FILLATRE, BENOÎT DUPONT DE DINECHIN, AUGUST 2021.
2020
- BOUNDING THE DELAYS OF THE MPPA NETWORK-ON-CHIP WITH NETWORK CALCULUS: MODELS AND BENCHMARKS. MARC BOYER, AMAURY GRAILLAT, BENOÎT DUPONT DE DINECHIN, JÖRN MIGGE. PERFORM. EVALUATION 143: 102124 (2020)
- “TOWARDS THE BASIC LINEAR ALGEBRA UNIT : REPLICATING MULTI-DIMENSIONAL FPUS TO ACCELERATE LINEAR ALGEBRA APPLICATIONS,” NICOLAS BRUNIE – 54TH ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS, AND COMPUTERS, 2020, PP. 1283-1290 (2020)
- DEEP LEARNING INFERENCE ON THE MPPA3 MANYCORE PROCESSOR. BENOIT DUPONT DE DINECHIN – EMBEDDED WORLD CONFERENCE 2020
- SCALING UP THE MEMORY INTERFERENCE ANALYSIS FOR HARD REAL-TIME MANY-CORE SYSTEMS. MAXIMILIEN DUPONT DE DINECHIN, MATHEUS SCHUH, MATTHIEU MOY, CLAIRE MAIZA, 2020
- A STUDY OF PREDICTABLE EXECUTION MODELS IMPLEMENTATION FOR INDUSTRIAL DATA-FLOW APPLICATIONS ON A MULTI-CORE PLATFORM WITH SHARED BANKED MEMORY. MATHEUS SCHUH, CLAIRE MAIZA, JOËL GOOSSENS, PASCAL RAYMOND, BENOÎT DUPONT DE DINECHIN. RTSS 2020
- CERTIFIED AND EFFICIENT INSTRUCTION SCHEDULING: APPLICATION TO INTERLOCKED VLIW PROCESSORS. CYRIL SIX, SYLVAIN BOULMÉ, DAVID MONNIAUX. PROC. ACM PROGRAM. LANG. 4(OOPSLA): 129:1-129:29 (2020)
2019
- “PRECISION ADAPTATION FOR FAST AND ACCURATE POLYNOMIAL EVALUATION GENERATION,” – N. BRUNIE, C. LAUTER AND G. REVY – 2019 IEEE 30TH INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS (ASAP), 2019, PP. 41-41
- “RESPONSE TIME ANALYSIS OF DATAFLOW APPLICATIONS ON A MANY-CORE PROCESSOR WITH SHARED-MEMORY AND NETWORK-ON-CHIP” AMAURY GRAILLAT, CLAIRE MAIZA, MATTHIEU MOY, PASCAL RAYMOND, BENOÎT DUPONT DE DINECHIN. RTNS 2019 / 27TH INTERNATIONAL CONFERENCE ON REAL-TIME NETWORKS AND SYSTEMS, TOULOUSE, FRANCE, NOVEMBER 2019.
- “CONSOLIDATING HIGH-INTEGRITY, HIGH-PERFORMANCE, AND CYBER-SECURITY FUNCTIONS ON A MANYCORE PROCESSOR” BENOÎT DUPONT DE DINECHIN, DAC ’19- PROCEEDINGS OF THE 56TH ANNUAL DESIGN AUTOMATION CONFERENCE, LAS VEGAS, NEVADA, JUNE 2019.
2018
- SEE ERROR-RATE EVALUATION OF AN APPLICATION IMPLEMENTED IN COTS MULTI/MANY-CORE PROCESSORS P. RAMOS ET AL. IEEE TRANSACTIONS ON NUCLEAR SCIENCE, INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, 2018
- “META-IMPLEMENTATION OF VECTORIZED LOGARITHM FUNCTION IN BINARY FLOATING-POINT ARITHMETIC,” H. DE LASSUS SAINT-GENIÈS, N. BRUNIE AND G. REVY, 2018 IEEE 29TH INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS (ASAP), 2018, PP. 1-8.
- DOL-BIP-CRITICAL: A TOOL CHAIN FOR RIGOROUS DESIGN AND IMPLEMENTATION OF MIXED-CRITICALITY MULTI-CORE SYSTEMS B. DUPONT DE DINECHIN ET AL. DESIGN AUTOMATION FOR EMBEDDED SYSTEMS PP 1–41, 2018
- PARALLEL CODE GENERATION OF SYNCHRONOUS PROGRAMS FOR A MANY-CORE ARCHITECTURE A. GRAILLAT, B. DUPONT DE DINECHIN ET AL. DATE 2018 – DESIGN, AUTOMATION AND TEST IN EUROPE, MARCH 2018, DRESDEN, GERMANY
- USING EXECUTION GRAPHS TO MODEL A PREFETCH AND WRITE BUFFERS AND ITS APPLICATION TO THE BOSTAN MPPA WEI-TSUN SUN ET AL. INTERNATIONAL CONFERENCE ON EMBEDDED REAL TIME SOFTWARE AND SYSTEMS (ERTS2 2018), TOULOUSE, FRANCE
- EMBEDDED RUNTIME FOR RECONFIGURABLE DATAFLOW GRAPHS ON MANYCORE ARCHITECTURES J. HASCOËT, B. DUPONT DE DINECHIN ET AL. PARMA-DITAM, JAN. 2018, MANCHESTER, UNITED KINGDOM
- COMPUTING ROUTES AND DELAY BOUNDS FOR THE NETWORK-ON-CHIP OF THE KALRAY MPPA2 PROCESSOR B. DUPONT DE DINECHIN, A. GRAILLAT ET AL. ERTS 2018 – 9TH EUROPEAN CONGRESS ON EMBEDDED REAL TIME SOFTWARE AND SYSTEMS, JAN. 2018, TOULOUSE, FRANCE
- “MANYCORE PROCESSOR FOR NEXT GENERATION INTELLIGENT VEHICLES”, NICOLAS BRUNIE – EMBEDDED MULTI-CORE CONFERENCE, JUNE 26-27 2018, MUNICH GERMANY
- “OVERVIEW OF ARITHMETIC AT KALRAY: METALIBM AND THE REST”, NICOLAS BRUNIE – ARIC SEMINAR, DECEMBER 6TH 2018, LYON, FRANCE
2017
- IMPROVING 3D LATTICE BOLTZMANN METHOD STENCIL WITH ASYNCHRONOUS TRANSFERS ON MANY-CORE PROCESSORS M. HO, B. DUPONT DE DINECHIN, JULIEN HASCOET ET AL. 36TH IEEE INTERNATIONAL PERFORMANCE COMPUTING AND COMMUNICATIONS CONFERENCE (IPCCC 2017), DEC. 2017, SAN DIEGO, UNITED STATES
- FEED-FORWARD ROUTING FOR THE WORMHOLE SWITCHING NETWORK-ON-CHIP OF THE KALRAY MPPA2-256 PROCESSOR B. DUPONT DE DINECHIN & A. GRAILLAT. 10TH INTERNATIONAL WORKSHOP ON NETWORK-ON-CHIP ARCHITECTURES (NOCARC 2017), BOSTON, MA, USA
- EXPLORING SCALABLE DATA ALLOCATION AND PARALLEL COMPUTING ON NOC-BASED EMBEDDED MANY CORES Y. MARUYAMA ET AL. 2017 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD), NOV. 5-8 , 2017, BOSTON, MA, USA
- QUANTIFYING WCET REDUCTION OF PARALLEL APPLICATIONS BY INTRODUCING SLACK TIME TO LIMIT RESOURCE CONTENTION S. MARTINEZ ET AL. INTERNATIONAL CONFERENCE ON REAL-TIME NETWORKS AND SYSTEMS (RTNS), 2017, OCT. 2017, GRENOBLE, FRANCE
- ASYNCHRONOUS ONE-SIDED COMMUNICATIONS AND SYNCHRONIZATIONS FOR A CLUSTERED MANYCORE PROCESSOR J. HASCOET, B. DUPONT DE DINECHIN, P. GUIRONNET DE MASSAS PIERRE & M. HO. 15TH IEEE/ACM SYMPOSIUM ON EMBEDDED SYSTEMS FOR REAL-TIME MULTIMEDIA (ESTIMEDIA 2017), SEOUL, SOUTH KOREA
- FAST MODULAR ARITHMETIC ON THE KALRAY MPPA-256 PROCESSOR FOR AN ENERGY-EFFICIENT IMPLEMENTATION OF ECM MASAHIRO ISHII ET AL. IEEE TRANSACTIONS ON COMPUTERS, INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, 2017, 66 (12), PP.2019-203
- HIERARCHICAL DATAFLOW MODEL FOR EFFICIENT PROGRAMMING OF CLUSTERED MANYCORE PROCESSORS J. HASCOËT, B. DUPONT DE DINECHIN ET AL. IEEE 28TH INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS (ASAP), SEATTLE, WA, 2017, PP. 137-142
- MODIFIED FUSED MULTIPLY AND ADD FOR EXACT LOW PRECISION PRODUCT ACCUMULATION N. BRUNIE. IEEE 24TH SYMPOSIUM ON COMPUTER ARITHMETIC (ARITH), LONDON, 2017, PP. 106-113
- MODELING INSTRUCTION CACHE AND INSTRUCTION BUFFER FOR PERFORMANCE ESTIMATION OF VLIW ARCHITECTURES USING NATIVE SIMULATION O. MATOUSSI & F. PÉTROT. DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, LAUSANNE, 2017, PP. 266-269
- NETWORK-ON-CHIP SERVICE GUARANTEES ON THE KALRAY MPPA-256 BOSTAN PROCESSOR B. DUPONT DE DINECHIN & A. GRAILLAT. 2ND INTERNATIONAL WORKSHOP ON ADVANCED INTERCONNECT SOLUTIONS AND TECHNOLOGIES FOR EMERGING COMPUTING SYSTEM (AISTECS 2017), STOCKHOLM, SWEDEN
- RADIATION EXPERIMENTS ON A 28 NM SINGLE-CHIP MANY-CORE PROCESSOR AND SEU ERROR-RATE PREDICTION V. RAY, C. JALIER, R. STEVENS & B. DUPONT DE DINECHIN. IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 64, NO. 1, PP. 483-490, JAN. 2017
2016
- RESPONSE TIME ANALYSIS OF SYNCHRONOUS DATA FLOW PROGRAMS ON A MANY-CORE PROCESSOR H. RIHANI ET AL. 24TH INTERNATIONAL CONFERENCE ON REAL-TIME NETWORKS AND SYSTEMS (RTNS 2016), PAGES 67-76
- VIRTUAL PROTOTYPING OF FLOATING POINT UNITS IN PROCEEDINGS OF THE 2016 WORKSHOP ON RAPID SIMULATION AND PERFORMANCE EVALUATION: METHODS AND TOOLS (RAPIDO ’16). GUILLAUME SARRAZIN, NICOLAS BRUNIE, AND FREDERIC PETROT. 2016.ASSOCIATION FOR COMPUTING MACHINERY, NEW YORK, NY, USA, ARTICLE 1, 1–6.
- MAPPING HARD REAL-TIME APPLICATIONS ON MANY-CORE PROCESSORS Q. PERRET ET AL. 24TH INTERNATIONAL CONFERENCE ON REAL-TIME AND NET-WORK SYSTEMS (RTNS 2016), OCT. 2016, BREST, FRANCE. RTNS ’16: PROCEEDINGS OF THE 24TH INTERNATIONAL CONFERENCE ON REAL-TIME NETWORKS AND SYSTEMS, PP. 235-244, 2016
- COMPUTING FLOATING-POINT LOGARITHMS WITH FIXED-POINT OPERATIONS J. LE MAIRE, N. BRUNIE ET AL. 23RD IEEE SYMPOSIUM ON COMPUTER ARITHMETIC, JUL 2016, SANTA CLARA, UNITED STATES. 2016
- MPI COMMUNICATION ON MPPA MANY-CORE NOC: DESIGN, MODELING AND PERFORMANCE ISSUES M. HO, B. DUPONT DE DINECHIN, J. REYBERT ET AL. PARCO 2015, SEP. 2015, EDINBURGH, UNITED KINGDOM. ADVANCES IN PARALLEL COMPUTING, VOLUME 27: PARALLEL COMPUTING: ON THE ROAD TO EXASCALE, 2016
- TEMPORAL ISOLATION OF HARD REAL-TIME APPLICATIONS ON MANY-CORE PROCESSORS Q. PERRET ET AL. RTAS: REAL-TIME EMBEDDED TECHNOLOGY & APPLICATIONS SYMPOSIUM, APR. 2016, VIENNE, AUSTRIA. REAL-TIME AND EMBEDDED TECHNOLOGY AND APPLICATIONS SYMPOSIUM (RTAS), 2016 IEEE
- PREDICTABLE COMPOSITION OF MEMORY ACCESSES ON MANY-CORE PROCESSORS Q. PERRET ET AL. 8TH EUROPEAN CONGRESS ON EMBEDDED REAL TIME SOFTWARE AND SYSTEMS (ERTS 2016), JAN. 2016, TOULOUSE, FRANCE
2015
- WCET ANALYSIS IN SHARED RESOURCES REAL-TIME SYSTEMS WITH TDMA BUSES H. RIHANI ET AL. RTNS 2015, NOV. 2015, LILLE, FRANCE. RTNS: 23RD INTERNATIONAL CONFERENCE ON REAL-TIME NETWORKS AND SYSTEMS, 2015, 23RD INTERNATIONAL CONFERENCE ON REAL-TIME NETWORKS AND SYSTEM
- THE SHIFT TO MULTICORES IN REAL-TIME AND SAFETY-CRITICAL SYSTEMS, 2015. INTERNATIONAL CONFERENCE ON HARDWARE/SOFTWARE CODESIGN AND SYSTEM SYNTHESIS (CODES+ISSS) B. DUPONT DE DINECHIN ET AL. AMSTERDAM, 2015, PP. 220-229
- IMPLEMENTATION OF A FAST FOURIER TRANSFORM ALGORITHM ONTO A MANYCORE PROCESSOR J. HASCOËT, B. DUPONT DE DINECHIN ET AL. CONFERENCE ON DESIGN & ARCHITECTURES FOR SIGNAL & IMAGE PROCESSING. SEP. 2015, CRACOW, POLAND
- CODE GENERATORS FOR MATHEMATICAL FUNCTIONS N. BRUNIE ET AL. 22ND IEEE SYMPOSIUM ON COMPUTER ARITHMETIC, JUNE 2015, LYON, FRANCE
- MIXED-CRITICALITY SCHEDULING ON CLUSTER-BASED MANYCORES WITH SHARED COMMUNICATION AND STORAGE RESOURCES B. DUPONT DE DINECHIN ET AL. REAL-TIME SYSTEMS (2015). VOL. 51, PP. 1-51