RECHERCHE ACADEMIQUE ET PUBLICATIONS

2021

• "A Qualitative Approach to Many-core Architecture” in "Multi-Processor System-on-Chip 1 Architectures", Benoît Dupont de Dinechin, Book ISBN: 9781789450217, March 2021.
• "Study and Comparison of Hardware Methods for Distributing Memory Bank Accesses in Many-core Architectures" in "Multi-Processor System-on-Chip 1 Architectures", Arthur Vianes, Frédéric Rousseau, Book ISBN : 9781789450217, March 2021.
• "Novel Arithmetics in Deep Neural Networks Signal Processing for Autonomous Driving: Challenges and Opportunities", Marco Cococcioni, Federico Rossi, Emanuele Ruffaldi, Sergio Saponara, Benoît Dupont de Dinechin, IEEE Signal Process. Mag. 38(1): 97-110, 2021.
• "Classification Error Approximation of a Compressed Linear Softmax Layer", Conference Paper - 29th European Signal Processing Conference (EUSIPCO 2021), Diana Resmerita, Rodrigo Cabral Farias, Lionel Fillatre, Benoît Dupont de Dinechin,  August 2021.

2020

• Bounding the delays of the MPPA network-on-chip with network calculus: Models and benchmarks. Marc Boyer, Amaury Graillat, Benoît Dupont de Dinechin, Jörn Migge. Perform. Evaluation 143: 102124 (2020)
• Deep Learning Inference on the MPPA3 Manycore Processor. Benoit Dupont de Dinechin - Embedded World Conference 2020
• Scaling Up the Memory Interference Analysis for Hard Real-Time Many-Core Systems. Maximilien Dupont de Dinechin, Matheus Schuh, Matthieu Moy, Claire Maiza, 2020
• A study of predictable execution models implementation for industrial data-flow applications on a multi-core platform with shared banked memory. Matheus Schuh, Claire Maiza, Joël Goossens, Pascal Raymond, Benoît Dupont de Dinechin. RTSS 2020
• Certified and efficient instruction scheduling: application to interlocked VLIW processors. Cyril Six, Sylvain Boulmé, David Monniaux. Proc. ACM Program. Lang. 4(OOPSLA): 129:1-129:29 (2020)

2018

• SEE error-rate evaluation of an application implemented in COTS Multi/Many-core processors P. Ramos et al. IEEE Transactions on Nuclear Science, Institute of Electrical and Electronics Engineers, 2018
• DOL-BIP-Critical: a tool chain for rigorous design and implementation of mixed-criticality multi-core systems B. Dupont de Dinechin et al. Design Automation for Embedded Systems pp 1–41, 2018
• Parallel Code Generation of Synchronous Programs for a Many-core Architecture A. Graillat, B. Dupont de Dinechin et al. DATE 2018 - Design, Automation and Test in Europe, March 2018, Dresden, Germany
• Using execution graphs to model a prefetch and write buffers and its application to the Bostan MPPA Wei-Tsun Sun et al. International Conference on Embedded Real Time Software and Systems (ERTS2 2018), Toulouse, France
• Embedded runtime for reconfigurable dataflow graphs on manycore architectures J. Hascoët, B. Dupont de Dinechin et al. PARMA-DITAM, Jan. 2018, Manchester, United Kingdom
• Computing Routes and Delay Bounds for the Network-on-Chip of the Kalray MPPA2 Processor B. Dupont de Dinechin, A. Graillat et al. ERTS 2018 - 9th European Congress on Embedded Real Time Software and Systems, Jan. 2018, Toulouse, France
•  "Manycore Processor for Next Generation Intelligent Vehicles", Nicolas Brunie - Embedded Multi-Core Conference, June 26-27 2018, Munich Germany
• "Overview of arithmetic at Kalray: metalibm and the rest", Nicolas Brunie - Aric seminar, December 6th 2018, Lyon, France

2017

• Improving 3D Lattice Boltzmann Method stencil with asynchronous transfers on many-core processors M. Ho, B. Dupont de Dinechin, Julien Hascoet et al. 36th IEEE International Performance Computing and Communications Conference (IPCCC 2017), Dec. 2017, San Diego, United States
• Feed-Forward Routing for the Wormhole Switching Network-on-Chip of the Kalray MPPA2-256 Processor B. Dupont de Dinechin & A. Graillat. 10th International Workshop on Network-on-Chip Architectures (NoCArc 2017), Boston, MA, USA
• Exploring Scalable Data Allocation and Parallel Computing on NoC-Based Embedded Many Cores Y. Maruyama et al. 2017 IEEE International Conference on Computer Design (ICCD), Nov. 5-8 , 2017, Boston, MA, USA
• Quantifying WCET reduction of parallel applications by introducing slack time to limit resource contention S. Martinez et al. International Conference on Real-Time Networks and Systems (RTNS), 2017, Oct. 2017, Grenoble, France
• Asynchronous One-Sided Communications and Synchronizations for a Clustered Manycore Processor J. Hascoet, B. Dupont de Dinechin, P. Guironnet de Massas Pierre & M. Ho. 15th IEEE/ACM Symposium on Embedded Systems for Real-Time Multimedia (ESTIMedia 2017), Seoul, South Korea
• Fast Modular Arithmetic on the Kalray MPPA-256 Processor for an Energy-Efficient Implementation of ECM Masahiro Ishii et al. IEEE Transactions on Computers, Institute of Electrical and Electronics Engineers, 2017, 66 (12), pp.2019-203
• Hierarchical Dataflow Model for efficient programming of clustered manycore processors J. Hascoët, B. Dupont de Dinechin et al. IEEE 28th International Conference on Application-specific Systems, Architectures and Processors (ASAP), Seattle, WA, 2017, pp. 137-142
• Modified Fused Multiply and Add for Exact Low Precision Product Accumulation N. Brunie. IEEE 24th Symposium on Computer Arithmetic (ARITH), London, 2017, pp. 106-113
• Modeling instruction cache and instruction buffer for performance estimation of VLIW architectures using native simulation O. Matoussi & F. Pétrot. Design, Automation & Test in Europe Conference & Exhibition, Lausanne, 2017, pp. 266-269
• Network-on-Chip Service Guarantees on the Kalray MPPA-256 Bostan Processor B. Dupont de Dinechin & A. Graillat. 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing System (AISTECS 2017), Stockholm, Sweden
• Radiation Experiments on a 28 nm Single-Chip Many-Core Processor and SEU Error-Rate Prediction V. Ray, C. Jalier, R. Stevens & B. Dupont de Dinechin. IEEE Transactions on Nuclear Science, vol. 64, no. 1, pp. 483-490, Jan. 2017

2016

• Response Time Analysis of Synchronous Data Flow Programs on a Many-core Processor H. Rihani et al. 24th International Conference on Real-Time Networks and Systems (RTNS 2016), pages 67-76
• Mapping hard real-time applications on many-core processors Q. Perret et al. 24th International Conference on Real-Time and Net-work Systems (RTNS 2016), Oct. 2016, Brest, France. RTNS ’16: Proceedings of the 24th International Conference on Real-Time Networks and Systems, pp. 235-244, 2016
• Computing floating-point logarithms with fixed-point operations J. Le Maire, N. Brunie et al. 23rd IEEE Symposium on Computer Arithmetic, Jul 2016, Santa Clara, United States. 2016
• MPI communication on MPPA Many-core NoC: design, modeling and performance issues M. Ho, B. Dupont de Dinechin, J. Reybert et al. ParCo 2015, Sep. 2015, Edinburgh, United Kingdom. Advances in Parallel Computing, Volume 27: Parallel Computing: On the Road to Exascale, 2016
• Temporal isolation of hard real-time applications on many-core processors Q. Perret  et al. RTAS: Real-Time Embedded Technology & Applications Symposium, Apr. 2016, VIENNE, Austria. Real-Time and Embedded Technology and Applications Symposium (RTAS), 2016 IEEE
• Predictable composition of memory accesses on many-core processors Q. Perret et al. 8th European Congress on Embedded Real Time Software and Systems (ERTS 2016), Jan. 2016, Toulouse, France

2015

• WCET analysis in shared resources real-time systems with TDMA buses H. Rihani et al. RTNS 2015, Nov. 2015, Lille, France. RTNS: 23rd International Conference on Real-Time Networks and Systems, 2015, 23rd International Conference on Real-Time Networks and System
• The shift to multicores in real-time and safety-critical systems, 2015. International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) B. Dupont de Dinechin et al. Amsterdam, 2015, pp. 220-229
• Implementation of a Fast Fourier Transform Algorithm onto a Manycore Processor J. Hascoët, B. Dupont de Dinechin et al. Conference on Design & Architectures for Signal & Image Processing. Sep. 2015, Cracow, Poland
• Code generators for mathematical functions N. Brunie et al. 22nd IEEE Symposium on Computer Arithmetic, June 2015, Lyon, France
• Mixed-criticality scheduling on cluster-based manycores with shared communication and storage resources B. Dupont de Dinechin et al. Real-Time Systems (2015). Vol. 51, pp. 1-51